RTL → GDSII | STA | CTS | Floorplanning | OpenLane
B.Tech ECE student focused on VLSI Physical Design. Experienced with RTL to GDSII using OpenLane and Sky130, with strong interest in timing closure and CTS.
CDC-safe FIFO using Gray-code pointers and synchronizers. Completed full PD flow with post-CTS timing closure.
Analyzed setup & hold violations and applied buffering and gate sizing to achieve closure.
Email: rajjoshi1220@gmail.com
GitHub: github.com/rajjoshi2009